I collaborate with IBM and Meta in my research. I also worked at AMD and Nvidia before.
Full-time Positions
- Nvidia,
Bangalore, India
ASIC Engineer
August'11 – June'12- Timing closure for GPU-GDDR5/DDR3 interface in 28 nm GPUs
- Automated STA framework for a 28nm SoC, Wayne
- I developed an automated Static Timing Analysis framework, using Perl, for USB 2.0 IO modules in SoCs.
- I used this framework to close timing on USB 2.0 IO modelus in the 28nm low power mobile SoC, Tegra 4.
Internships
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AMD Research,
Austin, USA
Research Coop
Mar'18 – May'18, May'17 – Dec'17- Distributed framework to manage heterogeneous computers
- I designed a modular framework to manage heterogeneous processors using robust control. I prototyped the proposed design on a multi-CPU + GPU machine at AMD.
- I filed for a patent through AMD, and published a paper at MICRO'19 based on this work.
- Distributed framework to manage heterogeneous computers
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Nvidia,
Bangalore, India
ASIC Intern
Spring'11
-
SPICE analysis framework for a GPU
- I developed a framework with SPICE, Perl and Tcl, for HSPICE analysis of multi voltage high speed Framebuffer IO paths in GF117, the first 28nm chip from Nvidia. GF117 was released as an entry level gaming GPU, GT 620M.
- The framework was used to validate the timing analysis of PrimeTime, an STA tool, from Synopsys.
- Partition/Block Timing closure for a GPU
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SPICE analysis framework for a GPU
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Indira Gandhi Centre for Atomic Research
(IGCAR),
Kalpakkam, India
Intern
Summer'09
- I was an intern with the group of Shri J Jayapandian, Head, Electronics & Instrumentation Section, Surface & Nanoscience Division, Materials Science Group, IGCAR.
- I worked on developing a micro-meter positioner read-out using virtual instrumentation techniques and a Programmable System on Chip (PSoC) based embedded system.