Abhishek Bhattacharjee

A. Bartlett Giamatti Professor of Computer Science

Yale University


abhishek at cs.yale.edu

I am interested in making computer systems efficient, both in terms of execution time and programming productivity. To this end, I build computer architectures, chips, compilers, and operating systems for the data center servers delivering on next-generation AI, and cutting-edge neurotechnologies.

My group has called attention to the rising overheads of memory address translation, and has proposed optimizations that are now widely used to mitigate these overheads. AMD, NVIDIA, RISC-V, Meta, and Linux have been influenced by my group's work on coalesced TLBs and translation contiguity, leading to integration of our ideas in billions of microprocessors and operating systems that comprise most modern data centers and many mobile systems. This work, and more, is summarized in my book on virtual memory and appendix to the classic Hennessy & Patterson textbook.

My group also builds full-fledged integrated computer systems for brain-computer interfaces. Our goal is to transform the treatment of neurological disorders and shed light on brain function via innovations in computing. Through our HALO and SCALO systems, we are taping out low power and flexible chips for brain interfaces. To learn more, check out my ASPLOS '23 keynote, and stay tuned for an upcoming report from a CCC visioning workshop on brain-computer interfaces that I organized.

I received the 2023 ACM SIGARCH Maurice Wilkes Award "for contributions to memory address translation used in widely available commercial microprocessors and operating systems". My research has received six Top Picks selections and two honorable mentions, a Best Paper Award at ISCA '23, a Distinguished Paper Award at ASPLOS '23, and a visiting CV Starr Fellowship at Princeton Neuroscience. I received Yale College's 2025 Dylan Hixon ‘88 Prize for teaching excellence in the natural sciences. I also received Yale Engineering's 2022 Ackerman Award for excellence in teaching and mentoring.

teaching & research

    Selected Talks

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    Catalyzing Computing for Brain-Computer Interfaces
    UC Berkeley EECS, May'25
    Utah Computer Science & Blackrock Neurotech, March '25
    Yale Center for Brain and Mind Health, Feb'25
    Synchron Distinguished Colloquium, Aug'24
    Princeton Precision Health Institute, June'24
    Northwestern Computer Science Distinguished Lecture Series, Nov'23
    Cornell Computer Systems Lab, Oct'23
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    Direct Mind-Machine Teaming
    ASPLOS'23 keynote
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    Machines that Help Heal the Brain
    Yale for Humanity Campaign, Nov'23
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    HALO: A Flexible and Low Power Processing Fabric for Brain-Computer Interfaces, Hot Chips'22
    Our HALO chip tape-out is detailed in the session on academic projects
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    Fast Address Translation in the Era of Big-Memory Servers
    AMD Research & Advanced Development, July'24
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    Efficient Data Tiering for Heterogeneous Memory Systems
    Meta AI and Systems Co-Design Summit, Oct'23
    • Selected Publications

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    Fiduciary AI for the Future of Brain-Technology Interactions
    Embedding fiduciary duties-loyalty, care, and confidentiality-directly into BCI-integrated brain foundation models
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    Scalable Far Memory: Balancing Faults and Evictions, SOSP'25
    Optimizations to improve scaling of data movement to far memory
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    Dataflow-Specific Algorithms for Resource-Constrained Scheduling and Memory Design, SPAA'25
    Weighted red-blue pebble games for memory design in power-constrained implantable BCIs
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    Foresee: A Modular and Open Framework to Explore Integrated Processing on Brain-Computer Interfaces, EMBC'25
    A design space exploration tool for BCI computer systems
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    Single Address Space FaaS with Jord, ISCA'25
    An exposition of Function-as-a-Service assist with single address space virtual memory
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    PULSE: Accelerating Distributed Pointer Traversals on Disaggregated Memory, ASPLOS'25
    Pointer chasing acceleration for disaggregated memory
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    Understanding Address Translation Scaling Behaviors Using Performance Counters, IISWC'24
    An exploration of address translation behavior as a function of application memory footprint
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    Characterizing Emerging Page Replacement Policies for Memory-Intensive Applications, IISWC'24
    An exploration of Linux's Multi-Generational LRU replacement policy
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    CryptoMMU: Enabling Scalable and Secure Access Control of Third-Party Accelerators, MICRO'23
    Best Paper Award Nominee
    Sandboxing accelerators using cryptographic approaches
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    Prefetching Using Principles of Hippocampal-Neocortical Interaction, HotOS'23
    Using principles of cognition to build leaner learned memory page prefetchers
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    SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing, ISCA'23
    Best Paper Award
    Selected for inclusion in IEEE Micro's Top Picks in Computer Architecture
    A distributed system of HALO chips in multiple brain implants
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    Imprecise Store Exceptions, ISCA'23
    On the implications of deeper memory hierarchies for precise exceptions
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    Mosaic Pages: Big TLB Reach with Small Pages, ASPLOS'23
    Distinguished Paper Award
    Selected for inclusion in IEEE Micro's Top Picks in Computer Architecture
    A theoretically-backed approach to virtual memory and memory translation
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    Distill: Domain-Specific Compilation for Cognitive Models, CGO'22
    Compiler tools for large-scale computational modeling of cognitive control in the human brain
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    MIND: In-Network Memory Management for Disaggregated Data Centers, SOSP'21
    Pushing virtual memory functionality into programmable network switches for memory disaggregation
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    Rebooting Virtual Memory with Midgard, ISCA'21
    A study of the benefits of making hardware aware of the concept of virtual memory areas
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    Hardware-Software Co-Design for Brain-Computer Interfaces, ISCA'20
    IEEE Micro's Top Picks in Computer Architecture
    Selected as part of the ISCA-50 retrospective program
    Check out a layout diagram of our HALO chips as well as their close-up and batch snaps
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    Translation Ranger: Operating System Support for Contiguity-Aware TLBs, ISCA'19
    Check out our kernel here
    Check out the status of our Linux patchset
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    Generic System Calls for GPUs, ISCA'18
    Honorable mention, IEEE Micro's Top Picks in Computer Architecture
    Released under the Radeon Open Compute project for ultrascale computing
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    Translation-Triggered Prefetching, ASPLOS'17
    IEEE Micro's Top Picks in Computer Architecture
    Best paper award nominee
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    COATCheck: Verifying Memory Ordering at the Hardware-OS Interface, ASPLOS'16
    IEEE Micro's Top Picks in Computer Architecture
    Our COATCheck tool is available here
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    Architectural Support for Address Translation on GPUs, ASPLOS'14
    IEEE Micro's Top Picks in Computer Architecture
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    COLT: Coalesced Large-Reach TLBs, MICRO'12
    Integrated in AMD chips, beginning with the Zen architecture
    • Textbooks

  • Link
    Architectural and Operating System Support for Virtual Memory
    Synthesis lecture monograph on introductory and more advanced virtual memory concepts
  • PDF
    Advanced Concepts on Address Translation

    Appendix L in "Computer Architecture: A Quantitative Approach" by Hennessy and Patterson

    • Teaching

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    Introduction to Systems Programming & Computer Organization (CPSC 323)
    Spring'20, Spring'21, Spring'22, Fall'22
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    Computer Architecture (CPSC 420/520, EENG 420, ENAS 820)
    Spring'23, Spring'24, Spring'25