Abhishek Bhattacharjee

A. Bartlett Giamatti Professor of Computer Science

Yale University


abhishek at cs.yale.edu

I build computer architectures, operating systems, compilers, and chips for emerging data center servers and brain computer interfaces.

My group has led the way in calling attention to the rising overheads of memory address translation, and has pioneered optimizations to mitigate these overheads. AMD has shipped over a billion Zen CPU cores using coalesced TLBs. NVIDIA has shipped tens of millions of GPUs with TLB support for translation contiguity. Billions of Linux operating systems integrate our large page migration code, and support folios, motivated by our translation contiguity work. We have also influenced page table formats for naturally-aligned power-of-two contiguity, supported in all RISC-V cores. Finally, our work on memory tiering has influenced the deployment of hundreds of thousands of Meta's servers. This, and more, is summarized in my book on virtual memory and appendix to the classic Hennessy & Patterson textbook.

My group is also leading the charge in making brain computer interfaces full-fledged computers with the processing horsepower to effectively treat neurological disorders, shed light on brain function, and augment human capability. Through our HALO and SCALO systems, we are taping out low power and flexible chips for brain interfaces. Check out my ASPLOS '23 keynote to learn more.

I received the 2023 ACM SIGARCH Maurice Wilkes Award "for contributions to memory address translation used in widely available commercial microprocessors and operating systems". My research has been recognized with six Top Picks selections and two honorable mentions, a Best Paper Award at ISCA '23, a Distinguished Paper Award at ASPLOS '23, a visiting CV Starr Fellowship at Princeton Neuroscience, and more. My teaching and mentoring have been recognized with the Yale SEAS Ackerman Award.

teaching & research

    Selected Talks

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    Catalyzing Computing for Brain-Computer Interfaces, Utah & Blackrock Neurotech, Jan '25
    Joint colloquium between Computer Science and Blackrock Neurotech
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    Catalyzing Computing for Brain-Computer Interfaces, Synchron, Aug '24
    Distinguished Seminar Series
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    Fast Address Translation in the Era of Big-Memory Servers, AMD, July '24
    AMD's Research & Advanced Development colloquium
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    Catalyzing Computing for Brain-Computer Interfaces, Princeton, June '24
    Precision Health Institute colloquium
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    Balancing Heterogeneity and Programmability Across Computing Scales, Princeton, Feb '24
    Computer Science colloquium
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    Balancing Heterogeneity and Programmability Across Computing Scales, NCSU, Jan '24
    Electrical & Computer Engineering colloquium
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    Machines that Help Heal the Brain, Yale for Humanity Campaign, Nov '23
    Featured speaker for "What Makes Us Human? Unlocking Secrets of the Brain, Mind, and Behavior"
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    Computer Architectures for Neural Interfaces, Northwestern, Nov '23
    Computer Science Distinguished Lecture Series
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    Computer Architectures for Neural Interfaces, Cornell, Oct '23
    Computer Systems Lab colloquium
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    Efficient Data Tiering for Heterogeneous Memory Systems, Meta, Oct '23
    Meta's AI and Systems Co-Design Summit
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    Direct Mind-Machine Teaming, ASPLOS '23
    Conference keynote talk
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    HALO: A Flexible and Low Power Processing Fabric for Brain-Computer Interfaces, Hot Chips '22
    Our HALO chip tape-out is detailed in the session on academic projects
    • Selected Publications

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    PULSE: Accelerating Distributed Pointer Traversals on Disaggregated Memory, ASPLOS '25
    Pointer chasing acceleration for disaggregated memory
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    Understanding Address Translation Scaling Behaviors Using Performance Counters, IISWC '24
    An exploration of address translation behavior as a function of application memory footprint
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    Characterizing Emerging Page Replacement Policies for Memory-Intensive Applications, IISWC '24
    An exploration of Linux's Multi-Generational LRU replacement policy
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    CryptoMMU: Enabling Scalable and Secure Access Control of Third-Party Accelerators, MICRO '23
    Best Paper Award Nominee
    Sandboxing accelerators using cryptographic approaches
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    Prefetching Using Principles of Hippocampal-Neocortical Interaction, HotOS '23
    Using principles of cognition to build leaner learned memory page prefetchers
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    SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing, ISCA '23
    Best Paper Award
    Selected for inclusion in IEEE Micro's Top Picks in Computer Architecture
    A distributed system of HALO chips in multiple brain implants
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    Imprecise Store Exceptions, ISCA '23
    On the implications of deeper memory hierarchies for precise exceptions
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    Mosaic Pages: Big TLB Reach with Small Pages, ASPLOS '23
    Distinguished Paper Award
    Selected for inclusion in IEEE Micro's Top Picks in Computer Architecture
    A theoretically-backed approach to virtual memory and memory translation
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    Distill: Domain-Specific Compilation for Cognitive Models, CGO '22
    Compiler tools for large-scale computational modeling of cognitive control in the human brain
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    MIND: In-Network Memory Management for Disaggregated Data Centers, SOSP '21
    Pushing virtual memory functionality into programmable network switches for memory disaggregation
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    Rebooting Virtual Memory with Midgard, ISCA '21
    A study of the benefits of making hardware aware of the concept of virtual memory areas
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    Hardware-Software Co-Design for Brain-Computer Interfaces, ISCA '20
    IEEE Micro's Top Picks in Computer Architecture
    Selected as part of the ISCA-50 retrospective program
    Check out a layout diagram of our HALO chips as well as their close-up and batch snaps
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    Translation Ranger: Operating System Support for Contiguity-Aware TLBs, ISCA '19
    Check out our kernel here
    Check out the status of our Linux patchset
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    Generic System Calls for GPUs, ISCA '18
    Honorable mention, IEEE Micro's Top Picks in Computer Architecture
    Released under the Radeon Open Compute project for ultrascale computing
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    Architectural Support for Address Translation on GPUs, ASPLOS '14
    IEEE Micro's Top Picks in Computer Architecture
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    COLT: Coalesced Large-Reach TLBs, MICRO '12
    Integrated in AMD chips, beginning with the Zen architecture
    • Textbooks

  • Link
    Architectural and Operating System Support for Virtual Memory
    Synthesis lecture monograph on introductory and more advanced virtual memory concepts
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    Advanced Concepts on Address Translation

    Appendix L in "Computer Architecture: A Quantitative Approach" by Hennessy and Patterson

    • Teaching

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    Introduction to Systems Programming & Computer Organization (CPSC 323)
    Spring 20, Spring 21, Spring 22, Fall 22
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    Computer Architecture (CPSC 420/520, EENG 420, ENAS 820)
    Spring 23, Spring 24, Spring 25