Abhishek Bhattacharjee

Professor of Computer Science

Yale University


abhishek at cs.yale.edu




I am a computer architect. I also study operating systems, compilers, and chips to validate hypotheses on architectural choices for systems ranging from data center servers to those used in neural engineering.

My group has worked on memory address translation for several years. AMD has shipped an estimated one billion Zen CPU cores using coalesced TLBs. NVIDIA has shipped tens of millions of GPUs with TLB optimizations for extreme translation contiguity. An estimated two billion Linux operating systems use our code to migrate 2MB pages starting with the 4.14 kernel. These results have, in turn, influenced RISC-V's NAPOT translation contiguity feature and Meta's page placement algorithms for tiered memory systems. All this, and more, is summarized in my book and appendix to the classic Hennessy & Patterson textbook.

We are also building computer systems that help treat neurological disorders and shed light on brain function. In our HALO project, we are taping out low power and flexible chips for neural interfaces. In our SCALO project, we are building a neural interface that decodes neural signals from multiple brain sites. Check out my ASPLOS '23 keynote to learn more about our work.

I received the 2023 ACM SIGARCH Maurice Wilkes Award "for contributions to memory address translation used in widely available commercial microprocessors and operating systems". My research has been recognized with six Top Picks selections and two honorable mentions, a Best Paper Award at ISCA '23, a Distinguished Paper Award at ASPLOS '23, a visiting CV Starr Fellowship at Princeton Neuroscience, and more. My teaching and mentoring have been recognized with the Yale SEAS Ackerman Award.

teaching & research

    Selected Talks

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    Balancing Heterogeneity and Programmability Across Computing Scales, U of Central Florida, Feb '24
    Computer Architecture Coordination colloquium
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    Balancing Heterogeneity and Programmability Across Computing Scales, Princeton, Feb '24
    Computer Science colloquium
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    Balancing Heterogeneity and Programmability Across Computing Scales, NCSU, Jan '24
    Electrical & Computer Engineering colloquium
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    Machines that Help Heal the Brain, Yale for Humanity Campaign, Nov '23
    Featured speaker for "What Makes Us Human? Unlocking Secrets of the Brain, Mind, and Behavior"
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    Computer Architectures for Neural Interfaces, Northwestern, Nov '23
    CS Distinguished Lecture Series
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    Computer Architectures for Neural Interfaces, Cornell, Oct '23
    Computer Systems Lab colloquium
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    Efficient Data Tiering for Heterogeneous Memory Systems, Meta, Oct '23
    Meta's AI and Systems Co-Design Summit
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    Virtual Memory for Post-Moore Servers, Intel, Sept '23
    Presented with collaborators at Intel's Transformative Server Architecture program
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    Direct Mind-Machine Teaming, ASPLOS '23
    Conference keynote talk
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    HALO: A Flexible and Low Power Processing Fabric for Brain-Computer Interfaces, Hot Chips '22
    Our HALO chip tape-out is detailed in the session on academic projects
  • Selected Publications

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    CryptoMMU: Enabling Scalable and Secure Access Control of Third-Party Accelerators, MICRO '23
    Best Paper Award Nominee
    Sandboxing accelerators using cryptographic approaches
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    Prefetching Using Principles of Hippocampal-Neocortical Interaction, HotOS '23
    Using principles of cognition to build leaner learned memory page prefetchers
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    SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing, ISCA '23
    Best Paper Award
    Selected for inclusion in IEEE Micro's Top Picks in Computer Architecture
    A distributed system of HALO chips in multiple brain implants
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    Imprecise Store Exceptions, ISCA '23
    On the implications of deeper memory hierarchies for precise exceptions
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    Mosaic Pages: Big TLB Reach with Small Pages, ASPLOS '23
    Distinguished Paper Award
    Selected for inclusion in IEEE Micro's Top Picks in Computer Architecture
    A theoretically-backed approach to virtual memory and memory translation
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    AstriFlash: A Flash-Based System for Online Services, HPCA '23
    A study on integrating Flash into the memory hierarchy
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    MIND: In-Network Memory Management for Disaggregated Data Centers, SOSP '21
    Pushing virtual memory functionality into programmable network switches for memory disaggregation
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    Hardware-Software Co-Design for Brain-Computer Interfaces, ISCA '20
    IEEE Micro's Top Picks in Computer Architecture
    Selected as part of the ISCA-50 retrospective program
    Check out a layout diagram of our HALO chips as well as their close-up and batch snaps
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    Translation Ranger: Operating System Support for Contiguity-Aware TLBs, ISCA '19
    Check out our kernel here
    Check out the status of our Linux patchset
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    Generic System Calls for GPUs, ISCA '18
    Honorable mention, IEEE Micro's Top Picks in Computer Architecture
    Released under the Radeon Open Compute project for ultrascale computing
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    Architectural Support for Address Translation on GPUs, ASPLOS '14
    IEEE Micro's Top Picks in Computer Architecture
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    COLT: Coalesced Large-Reach TLBs, MICRO '12
    Integrated in AMD chips, beginning with the Zen architecture
  • Textbooks

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    Architectural and Operating System Support for Virtual Memory
    Synthesis lecture monograph on introductory and more advanced virtual memory concepts
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    Advanced Concepts on Address Translation

    Appendix L in "Computer Architecture: A Quantitative Approach" by Hennessy and Patterson

  • Teaching

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    Introduction to Systems Programming & Computer Organization (CPSC 323)
    Spring 20, Spring 21, Spring 22, Fall 22
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    Computer Architecture (CPSC 420/520, EENG 420, ENAS 820)
    Spring 23, Spring 24