Abhishek Bhattacharjee

Associate Professor of Computer Science

Yale University


abhishek at cs.yale.edu

I am an Associate Professor at Yale CS and a member of the Wu Tsai Institute for the brain sciences. I study computer architectures, systems software, and their efficient layering. Before Yale CS, I was at Rutgers CS.

My students and I are experts on virtual memory. AMD uses our coalesced TLBs in its flagship Zen architecture. Between 2017 and end-2019, AMD shipped over 260 million Zen cores with coalesced TLBs. By end-2022, AMD shipped an estimated one billion Zen cores with coalesced TLBs. Starting with the Ampere architecture in mid-2020, NVIDIA has shipped an estimated 50 million GPUs with TLB optimizations to support extreme translation contiguity. Starting with the 4.14 kernel in end-2017, an estimated two billion Linux OSes use our code to migrate 2MB pages. This, and more, is summarized in my textbook and appendix to the classic Hennessy & Patterson textbook on computer architecture.

More recently, we have also been building computer systems that help treat neurological disorders, augment the healthy brain, and shed light on brain function. In our HALO project, we have architected and are taping out low power and flexible chips for brain-computer interfaces.

Our research has been recognized with four IEEE Micro Top Picks awards and two honorable mentions, an NSF CAREER award, the Chancellor's Award for Faculty Excellence in Research at Rutgers, a visiting CV Starr Fellowship at Princeton's Neuroscience Institute, and more. My teaching and mentoring have been recognized with the Yale SEAS Ackerman Award.

teaching & research

    Selected Publications & Talks

  • PDF
    Hull: A Hardware-Software Co-Designed Distributed System for Scalable Brain-Computer Interfacing, ISCA '23
    An accelerator-rich distributed network of brain implants
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    Imprecise Store Exceptions, ISCA '23
    On the implications of deeper memory hierarchies for precise exceptions
  • Link
    Direct Mind-Machine Teaming, ASPLOS '23
    Conference keynote talk
  • PDF
    Mosaic Pages: Big TLB Reach with Small Pages, ASPLOS '23
    A theoretically-backed approach to virtual memory and memory translation
  • PDF
    AstriFlash: A Flash-Based System for Online Services, HPCA '23
    A study on integrating Flash into the memory hierarchy
  • Link
    Computer Systems for Direct Communication with the Brain, ICCD '22
    Conference keynote talk
  • Link
    HALO: A Flexible and Low Power Processing Fabric for Brain-Computer Interfaces, Hot Chips '22
    Our HALO chip tape-out is detailed in the session on academic projects
  • PDF
    Distill: Domain-Specific Compilation for Cognitive Models, CGO '22
    Compiler tools for large-scale computational modeling of cognitive control in the human brain
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    MIND: In-Network Memory Management for Disaggregated Data Centers, SOSP '21
    Pushing virtual memory functionality into programmable network switches for memory disaggregation
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    Rebooting Virtual Memory with Midgard, ISCA '21
    A study of the benefits of making hardware aware of the concept of virtual memory areas
  • PDF
    KLOCs: Kernel-Level Object Contexts for Heterogeneous Memory Systems, ASPLOS '21
    Check out our experimental kernel here
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    Hardware-Software Co-Design for Brain-Computer Interfaces, ISCA '20
    IEEE Micro's Top Picks in Computer Architecture
    Check out a layout diagram of our HALO chips as well as their close-up and batch snaps
  • PDF
    Translation Ranger: Operating System Support for Contiguity-Aware TLBs, ISCA '19
    Check out our kernel here
    Check out the status of our Linux patchset
  • PDF
    Nimble Page Management for Tiered Memory Systems, ASPLOS '19
    Native transparent hugepage migration has been integrated into the Linux kernel
    Our experimental kernel is available here
  • PDF
    Generic System Calls for GPUs, ISCA '18
    Honorable mention, IEEE Micro's Top Picks in Computer Architecture
    Released under the Radeon Open Compute project for ultrascale computing
  • PDF
    Translation-Triggered Prefetching, ASPLOS '17
    IEEE Micro's Top Picks in Computer Architecture
    Best paper award nominee
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    COATCheck: Verifying Memory Ordering at the Hardware-OS Interface, ASPLOS '16
    IEEE Micro's Top Picks in Computer Architecture
    Our COATCheck tool is available here
  • PDF
    Architectural Support for Address Translation on GPUs, ASPLOS '14
    IEEE Micro's Top Picks in Computer Architecture
  • PDF
    COLT: Coalesced Large-Reach TLBs, MICRO '12
    Integrated in AMD chips, beginning with the Zen architecture
    • Textbooks

  • Link
    Architectural and Operating System Support for Virtual Memory
    Synthesis lecture monograph on introductory and more advanced virtual memory concepts
  • PDF
    Advanced Concepts on Address Translation

    Appendix L in "Computer Architecture: A Quantitative Approach" by Hennessy and Patterson

    • Courses

  • Link
    Introduction to Systems Programming & Computer Organization (CPSC 323)
    Spring 20, Spring 21, Spring 22, Fall 22
  • Link
    Computer Architecture (CPSC 420/520, EENG 420, ENAS 820)
    Spring 23