ABHISHEK BHATTACHARJEE

Associate Professor of Computer Science

Yale University


abhishek [at] cs.yale.edu




I run Yale's Systems Architecture Group, and we study computer architectures and systems software for platforms of all scales, from data center servers to implantable brain-computer interfaces. We are part of the Computer Systems Lab, and I am a Fellow of Grace Hopper College.

Much of our work has been on virtual memory, with contributions to translation contiguity, memory transistency, and GPU address translation. Our results have influenced real-world systems including coalesced TLBs, now in AMD's chips, and large page optimizations, now in Linux.

More recently, we have been building computer systems to help treat neurological disorders and advance the brain sciences. Our contributions include HALO, a flexible architecture for implantable brain-computer interfaces, and PsyNeuLink, a modeling environment for simulation of brain function.

Before Yale CS, I was an associate professor at Rutgers CS, a PhD student at Princeton, and an undergraduate student at McGill. Going even further back, I lived and studied in NYC, India, Italy, Malta, Myanmar, and Bangladesh.

teaching & research

    Recent Courses

  • INFO
    CPSC 323: Introduction to Systems Programming and Computer Organization
    Spring '20
  • INFO
    CPSC 436/536: The Hardware/Software Interface
    Fall '19
  • INFO
    CPSC 635: Topics on the Hardware/Software Interface
    Spring '19

  • Technical Monographs

  • PDF
    Advanced Concepts on Address Translation

    Appendix L in "Computer Architecture: A Quantitative Approach" by Hennessy and Patterson

  • PDF
    Architectural and Operating System Support for Virtual Memory
    Synthesis lecture monograph on introductory and more advanced virtual memory concepts

  • Selected Research

  • PDF
    Hardware-Software Co-Design for Brain-Computer Interfaces, ISCA '20
    HALO is a general-purpose brain implant chip for treating neurological disorders and studying the brain
    Check out a layout diagram of our HALO chip tape-out
  • PDF
    Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines, ASPLOS '20
    Check out VMware's blog post covering our work
    Our experimental kernel is available here
  • PDF
    Translation Ranger: Operating System Support for Contiguity-Aware TLBs, ISCA '19
    Check out our kernel here
    Translation Ranger is being discussed with Linux kernel developers
  • PDF
    Nimble Page Management for Tiered Memory Systems, ASPLOS '19
    Native transparent hugepage migration has been integrated into the Linux kernel
    Our experimental kernel is available here
  • PDF
    Generic System Calls for GPUs, ISCA '18
    Honorable mention, IEEE Micro's Top Picks in Computer Architecture
    Released under the Radeon Open Compute project for ultrascale computing
  • PDF
    Using Branch Predictors to Predict Brain Activity in Brain-Machine Implants, MICRO '17
    Honorable mention, IEEE Micro's Top Picks in Computer Architecture
  • PDF
    Translation-Triggered Prefetching, ASPLOS '17
    Best paper award nominee
    IEEE Micro's Top Picks in Computer Architecture
  • PDF
    COATCheck: Verifying Memory Ordering at the Hardware-OS Interface, ASPLOS '16
    IEEE Micro's Top Picks in Computer Architecture
    Our COATCheck tool is available here
  • PDF
    Large Pages and Lightweight Memory Management in Virtualized Environments: Can You Have it Both Ways?, MICRO '15
    Best paper award nominee
  • PDF
    Architectural Support for Address Translation on GPUs, ASPLOS '14
    IEEE Micro's Top Picks in Computer Architecture
  • PDF
    CoLT: Coalesced Large-Reach TLBs, MICRO '12
    Integrated in AMD chips, beginning with the Zen architecture