ABHISHEK BHATTACHARJEE

Associate Professor

Department of Computer Science

Yale University




I run the Systems Architecture Group within Yale's Computer Systems Lab. We work at the boundary between computer architecture and systems software.

We've worked on coalesced TLBs, which are now implemented in AMD's chips; superpage optimizations that we have integrated into the Linux kernel; and the compilation stack in the PsyNeuLink simulator for cognitive neuroscience.

Before Yale CS, I was on the Rutgers CS faculty from 2010 to 2018. I obtained my PhD from Princeton in 2010 and BEng from McGill in 2005.

MORE...

selected teaching and research

    Teaching Materials
  • PDF
    Advanced Concepts on Address Translation

    Appendix L in "Computer Architecture: A Quantitative Approach" by Hennessy and Patterson

  • PDF
    Architectural and Operating System Support for Virtual Memory
    Synthesis lecture monograph on basic and advanced virtual memory concepts

  • Selected Research Publications
  • PDF
    Nimble Page Management for Tiered Memory Systems, ASPLOS '19
    Native transparent hugepage migration has been integrated into the Linux kernel
    Our experimental kernel is available here
  • PDF
    Scalable Distributed Last-Level TLBs Using Low-Latency Interconnects, MICRO '18
  • PDF
    Generic System Calls for GPUs, ISCA '18
    Selected for honorable mention in IEEE Micro's Top Picks in Computer Architecture journal
    Released under the Radeon Open Compute project for ultrascale computing
  • PDF
    SEESAW: Using Superpages to Improve VIPT Caches, ISCA '18
  • PDF
    Scheduling Page Table Walks for Irregular GPU Applications, ISCA '18
  • PDF
    LATR: Lazy Translation Coherence, ASPLOS '18
  • PDF
    Using Branch Predictors to Predict Brain Activity in Brain-Machine Implants, MICRO '17
    Selected for honorable mention in IEEE Micro's Top Picks in Computer Architecture journal
  • PDF
    Hardware Translation Coherence for Virtualized Systems, ISCA '17
  • PDF
    Translation-Triggered Prefetching, ASPLOS '17
    Best paper award nominee
    Selected for inclusion in IEEE Micro's Top Picks in Computer Architecture journal
  • PDF
    Efficient Address Translation for Architectures with Multiple Page Sizes, ASPLOS '17
  • PDF
    COATCheck: Verifying Memory Ordering at the Hardware-OS Interface, ASPLOS '16
    Selected for inclusion in IEEE Micro's Top Picks in Computer Architecture journal
    Our COATCheck tool is available here
  • PDF
    Architectural Support for Address Translation on GPUs, ASPLOS '14
    Selected for inclusion in IEEE Micro's Top Picks in Computer Architecture journal
  • PDF
    CoLT: Coalesced Large-Reach TLBs, MICRO '12
    Integrated in AMD chips, beginning with the Zen architecture