ABHISHEK BHATTACHARJEE

Associate Professor of Computer Science

Yale University




I run Yale's Systems Architecture Group, and we study computer architectures, operating systems, and compilers. Through the lens of these topics, we integrate accelerators into programmable and efficient platforms at all scales, from servers for data centers to embedded devices for brain-computer interfaces. We are part of the Computer Systems Lab, and I am a Fellow of Grace Hopper College.

Our contributions include coalesced TLBs in AMD's chips, hugepage support in Linux, and GPU system calls in Radeon Open Compute. We are also the developers of the concept of memory transistency.

Before Yale CS, I was at Rutgers CS as a faculty member, Princeton for my PhD, and McGill for my BEng.

selected teaching and research

    Teaching Materials
  • PDF
    Advanced Concepts on Address Translation

    Appendix L in "Computer Architecture: A Quantitative Approach" by Hennessy and Patterson

  • PDF
    Architectural and Operating System Support for Virtual Memory
    Synthesis lecture monograph on basic and advanced virtual memory concepts

  • Selected Research Publications
  • PDF
    Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines, ASPLOS '20
    Check out VMware's blog post covering our work
    Our experimental kernel is available here
  • PDF
    Translation Ranger: Operating System Support for Contiguity-Aware TLBs, ISCA '19
    Check out our kernel here
    We are working on patching Translation Ranger into the mainline Linux kernel
  • PDF
    Nimble Page Management for Tiered Memory Systems, ASPLOS '19
    Native transparent hugepage migration has been integrated into the Linux kernel
    Our experimental kernel is available here
  • PDF
    Generic System Calls for GPUs, ISCA '18
    Selected for honorable mention in IEEE Micro's Top Picks in Computer Architecture journal
    Released under the Radeon Open Compute project for ultrascale computing
  • PDF
    Using Branch Predictors to Predict Brain Activity in Brain-Machine Implants, MICRO '17
    Selected for honorable mention in IEEE Micro's Top Picks in Computer Architecture journal
  • PDF
    Translation-Triggered Prefetching, ASPLOS '17
    Best paper award nominee
    Selected for inclusion in IEEE Micro's Top Picks in Computer Architecture journal
  • PDF
    COATCheck: Verifying Memory Ordering at the Hardware-OS Interface, ASPLOS '16
    Selected for inclusion in IEEE Micro's Top Picks in Computer Architecture journal
    Our COATCheck tool is available here
  • PDF
    Large Pages and Lightweight Memory Management in Virtualized Environments: Can You Have it Both Ways?, MICRO '15
    Best paper award nominee
  • PDF
    Architectural Support for Address Translation on GPUs, ASPLOS '14
    Selected for inclusion in IEEE Micro's Top Picks in Computer Architecture journal
  • PDF
    CoLT: Coalesced Large-Reach TLBs, MICRO '12
    Integrated in AMD chips, beginning with the Zen architecture