Abhishek Bhattacharjee

Associate Professor of Computer Science

Yale University


abhishek at cs.yale.edu

I am an Associate Professor of CS at Yale, a member of its Computer Systems Lab and Wu Tsai Institute for cognition, as well as a Fellow at Grace Hopper College.

My research and teaching interests focus on computer architectures, systems software, and their efficient layering for both classical systems as well as those used for and inspired by the brain sciences.

My group has spent over a decade uncovering the challenges imposed on the virtual memory abstraction by advances in memory subsystems and the advent of hardware accelerators. We have laid the foundation for translation contiguity and memory transistency, proposed TLB coalescing, shared TLBs, better MMU caches, faster GPU address translation, efficient translation coherence, optimizations for large pages, rack-scale distributed shared memory, and more. These results and the body of work that they have enabled other groups to pursue are summarized in my textbook. Our results have influenced virtual memory implementation on real-world systems. Coalesced TLBs have been implemented in AMD's chips, our large page migration optimizations are now in Linux, and our work on generating translation contiguity is under active development in the Linux community.

We are also building computer systems to help treat neurological disorders, enable direct brain-computer interfacing, accelerate scientific discovery of the brain, and are also using techniques from the cognitive sciences to build better computer systems. In our HALO project, we are building low power and flexible chips for brain-computer interfaces. In our Distill project, we have built a compiler for large-scale computational modeling of cognitive control in the human brain.

My group's research has been recognized with four IEEE Micro Top Picks awards, two IEEE Micro Top Picks honorable mentions, an NSF CAREER award, the Chancellor's Award for Faculty Excellence in Research at Rutgers, where I was previously on the faculty, a visiting CV Starr Fellowship at Princeton's Neuroscience Institute, where I spent my post-tenure sabbatical, and more. My teaching and mentoring have been recognized with the Yale SEAS Ackerman Award.

teaching & research

    Selected Manuscripts

  • PDF
    Distill: Domain-Specific Compilation for Cognitive Models, CGO '22
    Compiler tools for large-scale computational modeling of cognitive control in the human brain
  • PDF
    MIND: In-Network Memory Management for Disaggregated Data Centers, SOSP '21
    Pushing virtual memory functionality into programmable network switches for memory disaggregation
  • PDF
    Rebooting Virtual Memory with Midgard, ISCA '21
    A study of the benefits of injecting the virtual memory area abstraction into hardware
  • PDF
    KLOCs: Kernel-Level Object Contexts for Heterogeneous Memory Systems, ASPLOS '21
    Check out our experimental kernel here
  • PDF
    Fast Local Page-Tables for Virtualized NUMA Servers with vMitosis, ASPLOS '21
    Check out our experimental kernel here
  • PDF
    Hardware-Software Co-Design for Brain-Computer Interfaces, ISCA '20
    IEEE Micro's Top Picks in Computer Architecture
    Check out a layout diagram of our HALO chips as well as their close-up and batch snaps
  • PDF
    Translation Ranger: Operating System Support for Contiguity-Aware TLBs, ISCA '19
    Check out our kernel here
    Check out the status of our Linux patchset
  • PDF
    Nimble Page Management for Tiered Memory Systems, ASPLOS '19
    Native transparent hugepage migration has been integrated into the Linux kernel
    Our experimental kernel is available here
  • PDF
    Generic System Calls for GPUs, ISCA '18
    Honorable mention, IEEE Micro's Top Picks in Computer Architecture
    Released under the Radeon Open Compute project for ultrascale computing
  • PDF
    Translation-Triggered Prefetching, ASPLOS '17
    IEEE Micro's Top Picks in Computer Architecture
    Best paper award nominee
  • PDF
    COATCheck: Verifying Memory Ordering at the Hardware-OS Interface, ASPLOS '16
    IEEE Micro's Top Picks in Computer Architecture
    Our COATCheck tool is available here
  • PDF
    Architectural Support for Address Translation on GPUs, ASPLOS '14
    IEEE Micro's Top Picks in Computer Architecture
  • PDF
    COLT: Coalesced Large-Reach TLBs, MICRO '12
    Integrated in AMD chips, beginning with the Zen architecture
    • Technical Monographs

  • PDF
    Architectural and Operating System Support for Virtual Memory
    Synthesis lecture monograph on introductory and more advanced virtual memory concepts
  • PDF
    Advanced Concepts on Address Translation

    Appendix L in "Computer Architecture: A Quantitative Approach" by Hennessy and Patterson

    • Courses

  • Link
    Introduction to Systems Programming & Computer Organization (CPSC 323)
    Spring 20, Spring 21, Spring 22, Fall 22
  • Link
    Computer Architecture (CPSC 420/520, EENG 420, ENAS 820)
    Spring 23