ABHISHEK BHATTACHARJEE

Associate Professor

Department of Computer Science

Yale University

I run the Systems Architecture Group within Yale's Computer Systems Lab. We build architectures and systems software for data centers, as well as systems that interface with, and that improve our understanding of the brain.

Our results include coalesced TLBs, now used in AMD's chips; TLB coherence optimizations that have influenced Qualcomm's chips; hugepage support that we have integrated into Linux; and the GPU system call interface in Radeon Open Compute.

I teach courses on topics at the interface of architecture, operating systems, and compilers. I am also a Fellow of Grace Hopper College. Before Yale CS, I was on the Rutgers CS faculty. I completed my PhD from Princeton, and my BEng from McGill.

selected teaching and research

    Teaching Materials
  • PDF
    Advanced Concepts on Address Translation

    Appendix L in "Computer Architecture: A Quantitative Approach" by Hennessy and Patterson

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    Architectural and Operating System Support for Virtual Memory
    Synthesis lecture monograph on basic and advanced virtual memory concepts

    • Selected Research Publications
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    Translation Ranger: Operating System Support for Contiguity-Aware TLBs, ISCA '19
    Check out our kernel here and some other thoughts
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    Nimble Page Management for Tiered Memory Systems, ASPLOS '19
    Native transparent hugepage migration has been integrated into the Linux kernel
    Our experimental kernel is available here
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    TLB Shootdown Mitigation for Low-Power Many-Core Servers with L1 Virtual Caches, CAL '18
    Basis for TLB coherence in Qualcomm's chips, beginning with the Centriq architecture
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    Scalable Distributed Last-Level TLBs Using Low-Latency Interconnects, MICRO '18
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    Generic System Calls for GPUs, ISCA '18
    Selected for honorable mention in IEEE Micro's Top Picks in Computer Architecture journal
    Released under the Radeon Open Compute project for ultrascale computing
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    SEESAW: Using Superpages to Improve VIPT Caches, ISCA '18
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    Scheduling Page Table Walks for Irregular GPU Applications, ISCA '18
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    LATR: Lazy Translation Coherence, ASPLOS '18
    Our experimental kernel is available here
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    Using Branch Predictors to Predict Brain Activity in Brain-Machine Implants, MICRO '17
    Selected for honorable mention in IEEE Micro's Top Picks in Computer Architecture journal
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    Hardware Translation Coherence for Virtualized Systems, ISCA '17
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    Translation-Triggered Prefetching, ASPLOS '17
    Best paper award nominee
    Selected for inclusion in IEEE Micro's Top Picks in Computer Architecture journal
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    Efficient Address Translation for Architectures with Multiple Page Sizes, ASPLOS '17
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    COATCheck: Verifying Memory Ordering at the Hardware-OS Interface, ASPLOS '16
    Selected for inclusion in IEEE Micro's Top Picks in Computer Architecture journal
    Our COATCheck tool is available here
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    Large Pages and Lightweight Memory Management in Virtualized Environments: Can You Have it Both Ways?, MICRO '15
    Best paper award nominee
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    Architectural Support for Address Translation on GPUs, ASPLOS '14
    Selected for inclusion in IEEE Micro's Top Picks in Computer Architecture journal
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    CoLT: Coalesced Large-Reach TLBs, MICRO '12
    Integrated in AMD chips, beginning with the Zen architecture