Abhishek Bhattacharjee

Associate Professor of Computer Science

Yale University


he, him, his

abhishek [at] cs.yale.edu

I am an Associate Professor of Computer Science at Yale University. I am a member of the Computer Systems Lab, the Interdepartmental Neuroscience Program, and the inaugural steering committee of the Wu Tsai Institute for neuroscience. I am also a Fellow of Grace Hopper College.

My group's expertise is in the principled and efficient layering of computer systems. Effective layering through the right abstractions gives software developers a stable and familiar programming model, even while the underlying architecture is augmented via innovations in general-purpose execution, domain-specific acceleration, and new memory technologies.

My group has spent over a decade uncovering the challenges imposed on the virtual memory abstraction by larger and more heterogeneous memories as well as domain-specific hardware acceleration. To address these challenges, we have proposed translation contiguity and coalescing, shared TLBs, better MMU caches, faster GPU address translation, intermediate address spaces, efficient translation coherence, optimizations for large pages and more. We have also explored the specification and implementation of the hardware and software components responsible for virtual memory via our work on memory transistency. These results and the body of work that they have enabled other groups to pursue are summarized in my recently-published textbook. Our results have also influenced virtual memory implementation on real-world systems. Coalesced TLBs have been implemented in AMD's chips, our large page migration optimizations are now in Linux, and our work on generating even larger pages is under active development in the Linux community.

More recently, we have also built computer systems that advance the brain sciences to help treat neurological disorders, bridge the divide between the ditigal world and neurological systems, and offer a path towards more explainable human-like AI. In our HALO project, we are building ultra-low-power and flexible chips for brain-computer interfaces and evaluating them using data collected on non-human primates and epilepsy patients.

From 2010 to 2018, I was an Associate Professor of Computer Science at Rutgers University. In 2016, I was a visiting CV Starr Fellow at Princeton University's Neuroscience Institute. I received my PhD from Princeton University and my undergraduate degree from McGill University.

teaching & research

    Selected Articles

  • Link
    Race Logic Presents a Novel Form of Encoding: A Technical Perspective, CACM '21
    A technical perspective on CACM's research highlights paper on race logic
  • PDF
    Paging and the Address Translation Problem, SPAA '21
    This paper formulates the translation problem in a manner amenable to algorithmic analysis
  • PDF
    Rebooting Virtual Memory with Midgard, ISCA '21
    A study of the benefits of injecting the virtual memory area abstraction into hardware
  • PDF
    KLOCs: Kernel-Level Object Contexts for Heterogeneous Memory Systems, ASPLOS '21
    Check out our experimental kernel here
  • PDF
    Fast Local Page-Tables for Virtualized NUMA Servers with vMitosis, ASPLOS '21
    Check out our experimental kernel here
  • PDF
    Hardware-Software Co-Design for Brain-Computer Interfaces, ISCA '20
    IEEE Micro's Top Picks in Computer Architecture
    Check out a layout diagram of our HALO chips as well as their close-up and batch snaps
  • PDF
    Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines, ASPLOS '20
    Check out VMware's blog post covering our work
    Our experimental kernel is available here
  • PDF
    Translation Ranger: Operating System Support for Contiguity-Aware TLBs, ISCA '19
    Check out our kernel here
    Check out the status of our Linux patchset
  • PDF
    Nimble Page Management for Tiered Memory Systems, ASPLOS '19
    Native transparent hugepage migration has been integrated into the Linux kernel
    Our experimental kernel is available here
  • PDF
    Generic System Calls for GPUs, ISCA '18
    Honorable mention, IEEE Micro's Top Picks in Computer Architecture
    Released under the Radeon Open Compute project for ultrascale computing
  • PDF
    Translation-Triggered Prefetching, ASPLOS '17
    IEEE Micro's Top Picks in Computer Architecture
    Best paper award nominee
  • PDF
    COATCheck: Verifying Memory Ordering at the Hardware-OS Interface, ASPLOS '16
    IEEE Micro's Top Picks in Computer Architecture
    Our COATCheck tool is available here
  • PDF
    Architectural Support for Address Translation on GPUs, ASPLOS '14
    IEEE Micro's Top Picks in Computer Architecture
  • PDF
    CoLT: Coalesced Large-Reach TLBs, MICRO '12
    Integrated in AMD chips, beginning with the Zen architecture
    • Technical Monographs

  • PDF
    Architectural and Operating System Support for Virtual Memory
    Synthesis lecture monograph on introductory and more advanced virtual memory concepts
  • PDF
    Advanced Concepts on Address Translation

    Appendix L in "Computer Architecture: A Quantitative Approach" by Hennessy and Patterson

    • Currently Teaching

  • Link
    CPSC 323: Introduction to Systems Programming and Computer Organization
    Spring '20, Spring '21, Spring '22